1. Field of the Invention
This invention generally relates to semiconductor devices and methods of fabricating the same and, more specifically, to a semiconductor device having a field effect transistor (hereinafter referred to as “transistor”) and a method of fabricating the same.
2. Description of the Related Art
As a design rule is scaled down due to high-integration of semiconductor devices, many problems occur in planar transistors having horizontal channels so that there is a limitation to scaling down the size of the planar transistors. A short channel effect and a drain induced barrier lowering (DIBL) characteristic are exacerbated with scaling down of the planar transistors.
On the other hand, due to a recent trend towards high integration of semiconductor devices, transistors become further smaller, yet require fast speed. Thus, there is a need to increase a driving current of transistors. In other words, with high-integration and high-speed of the semiconductor devices, a transistor having small size and a large driving current has been heavily required.
Recently, in order to solve these problems, FinFET is disclosed in “2002 Symposium On VLSI Technology Digest of Technical Paper” entitled in “35 nm CMOS FinFETs” by Fu-Liang Yang et al. According to this, a gate electrode crossing a fin formed in a buried oxide layer of a silicon-on-insulator (SOI) substrate is formed. Impurity ions are implanted using a gate electrode as a mask. As a result, source/drain regions are formed in the fin at both sides of the gate electrode.
In the above-mentioned method, the source/drain regions are formed by an impurity implantation method. Now that impurities are implanted using an average projection range, the concentration of impurities may not be conformal according to the depth of the fin. In addition, since impurities are diffused randomly due to a thermal process for activation, the channel length may be changed according to a position. In addition, since the concentration of impurities is changed according to a position, the resistance of source/drain regions may be changed depending on the position. As a result, a current amount may be changed by a position of a channel region. If these phenomena are present, the channel length may be shortened because a channel is formed at only a portion of the channel region. That is, the driving current amount of transistors may be reduced. Additionally, if the channel lengths of the channel region are not constant, a leakage current may occur under a threshold voltage, and a channel region that requires a higher threshold voltage may exist. Therefore, on-off characteristic of transistors may be degraded.